Flash memory devices have been known for many years. Standard flash memory devices known in the art store data in a memory array, arranged in groups, called pages and/or blocks.
An example of a NAND flash memory device known in the art is Samsung Electronics device No. K9K4G08U1M. The Data Sheet (herein under—DS) of this device is incorporated by reference for all purposes as if fully set forth herein.
When exchanging data with a flash memory, an entire data page is usually written to the memory array or read out of it simultaneously, within one operation, from/to an internal buffer (or register) called a page buffer. A Host device, which the flash memory device is connected to, transfers the data to/from this page buffer.
The process of reading data from the flash memory device is carried out in two phases. In the first phase, data is transferred from the memory array to the page buffer of the flash memory device. In the second phase, data is transferred from the page buffer to the Host device.
The process of writing data to the flash memory device is carried out in two phases as well, such that in the first phase data is transferred from the Host device to the page buffer of the flash memory device and in the second phase data is transferred from the page buffer to the memory array.
Data transfer between the Host device and the page buffer is controlled by the Host device's hardware and/or software modules, and so the start and finish of this data transfer is directly controlled by these modules. However, the data transfer between the page buffer and the memory array is usually performed autonomously by the flash memory device, without intervention of the Host device. Therefore, the Host device's hardware and/or software modules are not aware of such transfer timing.
Because the data transfer between the page buffer and the memory array is time consuming (this phase lasts between tens to hundreds of microseconds), a special notification of a busy memory array is provided to the Host device. This notification is implemented as a “Ready/Busy” hardware signal, produced by the flash memory device and monitored by the Host device.
On top of the implementation of a hardware signal, the above mentioned notification of a busy memory array may further be available to the Host device software within status information via a “status register”.
For example, the hardware signal may generate an interrupt to the Host device upon completion of an operation, indicating that the flash memory device is ready for executing a new operation or, alternatively, the Host device's software module may poll the memory status register, waiting for this event.
The time spent for data exchange between the Host device and the flash memory device includes both Host ⇄ Buffer and Buffer ⇄ Memory Array transfer periods. As the data page size of existing flash memory devices increases, the Host ⇄ Buffer transfer time increases as well, and becomes comparable to the Buffer ⇄ Memory Array transfer time. For example, in a NAND flash memory device known in the art having a 2 KByte data page, the Host ⇄ Buffer transfer time is typically 50 to 100 microseconds per page, while Buffer ← Memory Array page read time is 20 to 50 microseconds per page and Buffer → Memory Array page program (write) time is 200 to 800 microseconds per page.
Therefore, in order to increase the system's throughput, some flash memory devices include an additional data buffer —a cache buffer for enabling a simultaneous data transfer between the Host device and this cache buffer and between the page buffer and the memory array.
It should be noted, that the NAND flash memory device whose data sheet is incorporated by reference herein implements a cache buffer for page programming only, however, there are other devices, which use it for a read operation as well.
In order to provide the Host device with the necessary transfer timing information and to achieve time efficiency, existing flash memory devices which include such a cache buffer include two logical “Ready/Busy” indications. The first indication, defined “Cache Ready/Busy” (or just “Ready/Busy”), is for indicating the availability of the cache buffer regarding the data transfer. The second indication, defined “True Ready/Busy”, is for indicating the current state of the memory array.
Practically, Host devices need to use both indications. While the “Cache Ready/Busy” indication is used to trigger next data transfer in a series, the “True Ready/Busy” indication is used to indicate whether the current operation running in the flash memory device has finished, the memory array is free, and a different operation may be started. This may happen when there is a need to switch from page read to page program or vice versa, or when the application needs to know that the current page programming indeed finished (page data is in the memory array, not only in a buffer) and next step in the application may start.
However, in flash memory devices known in the art only the “Cache Ready/Busy” indication is handled in a “hardware manner” (i.e. provided as a hardware “Ready/Busy” signal), by generating an interrupt to the application, as an example, whereas the “True Ready/Busy” indication is only polled by the Host device's software module, thus increasing the complexity of this module and decreasing its flexibility and time-efficiency.
One option to handle this situation is to implement the two logical “Ready/Busy” indications to be output by the flash memory device as hardware signals.
However, such an approach is impractical, because it violates the standard NAND flash interface and introduces lack of compatibility to similar devices which do not include a cache.
Existing methods for monitoring operation of flash memory devices do not implement the two logical “Ready/Busy” indications in a “hardware” manner.
There is thus a widely recognized need for, and it would be highly advantageous to have, a flash memory device and method for monitoring operation of the flash memory device, which is an alternative approach to prior art techniques, such that the flash memory device is compliant to a standard NAND flash interface.